1. Field of the Invention
The present invention relates generally to manufacturing semiconductor processing devices. More specifically, the present invention pertains to a self-planarization technique.
2. Description of Related Art
During the process of manufacturing semiconductor devices, electrically conductive materials patterned in electrical circuitry are layered over a semiconductor substrate. The electrically conductive materials, such as copper, are in different and non-contiguous planes. Vias or pathways connect the various layers of electrically conductive materials. An insulator or interlayer dielectric is placed between the separate planes of conductive material within the vias and also within the trenches and the circuit pattern of a layer of conductive material. Moreover, interconnects that are a conductive connection between two or more semiconductor devices are also formed.
In general, an interconnect can be formed by first depositing a metal into an opening or trench formed in an interlayer dielectric. The metal is typically planarized using chemical-mechanical polishing (CMP), which has a chemical component (e.g., slurries) and a mechanical component (e.g., a polishing pad). A balance between these two components is necessary to obtain good results. In general, excess metal (deposited outside of the opening) is polished (or removed) using a CMP process until the top surface of the metal is substantially planar with the interlayer dielectric. Unfortunately, wide metal structures (e.g., with a width of tens of microns) formed from a CMP process suffer from a phenomena termed "dishing" in which the surface of the metal is recessed below the interlayer dielectric in a dish or bowl shape. This degrades device performance and reliability.
An example of "dishing" can be seen in a prior art embodiment shown in FIGS. 1A, 1B, 1C. In FIG. 1A, a metal layer 103 is conformally deposited into narrow lines 107 and wide metal line 105, which are patterned into interlayer dielectric (ILD) 101. ILD 101 is disposed over a substrate 100. Substrate 100 typically contains active and passive semiconductor devices, at and within substrate 100. The substrate 100 can also be one of the layers in a multi-level interconnect.
Next, as shown in FIG. 1B, a CMP process is applied. Metal layer 103 is pre-planarized over narrow lines 107 but not over wide metal line 105. Because wide metal line 105 is wider than the thickness of deposited metal layer 103, the height of conductive layer 103 formed over wide metal line 105 is lower than its height over narrow lines 107. Consequently, areas with narrow features (e.g., narrow lines 107) will be cleared of the metal overburden more slowly than areas with wide features (e.g., wide metal line 105). As a result, the overburden is removed first from a wide feature, such as wide metal line 105 resulting in more overpolishing of wide metal line 105 than of narrow lines 107.
FIG. 1C illustrates the overpolish step, which is necessary to insure that the portion of metal layer 103 disposed above ILD 101 is removed. In general, the longer the overpolish period, then the greater the degree of dishing. During the overpolish step, the polish pad usually reaches (or "squeezes") into wide metal line 105 to remove material within the recess resulting in dishing. In contrast, narrow lines 107 are polished without any undesirable dishing. The polish pad does not remove material within the recess in narrow lines 107, which allows a planar formation of metal layer 103 over narrow lines 107.
Thus, it is desirable to minimize or reduce dishing during the chemical-mechanical polishing of a wide integrated circuit feature.